INMOS Technical Note 29: Dual Inline Transputer Modules (TRAMS)

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Dual Inline Transputer Modules (TRAMS)

Paul Walker

19 pages.

1. Introduction
2. Functional description
2.1 Pinout of Size1 module
2.2 Pinout of larger sized modules
2.3 TRAMs with more than one transputer
2.4 Extra pins
2.5 Subsystem signals driven from a TRAM
2.6 Memory parity
2.7 Memory map
3. Electrical description
3.1 Link outputs
3.2 Link inputs
3.3 notError output
3.4 Reset and analyse inputs
3.5 Clock input
3.6 notError input to subsystem
3.7 GND, VCC
4. Mechanical description
4.1 Width and length
4.2 Virtual dimensions
4.3 Direction of cooling
5. TRAM pins and sockets
5.1 Stackable socket
5.2 Through-board sockets
5.3 Subsystem pins and sockets
5.4 Motherboard sockets
6. Mechanical retention of TRAMs
A. Profile drawings


Reference Number :

Date Published : 10th December 1987

Manufacturer : INMOS

Platform : Transputer

 

 

 

 

 

This exhibit has a reference ID of CH40213. Please quote this reference ID in any communication with the Centre for Computing History. 		 

INMOS Technical Note 29: Dual Inline Transputer Modules (TRAMS)

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