The Memory Controller (MEMC) acts as the interface between the ARM (Acorn RISC Machine) processor,  Video Controller (VIDC), I/O Controllers (including IOC), memories (ROM) and Dynamic memory devices (DRAM), providing all the critical system timing signals.

Up to 4MBytes of DRAM may be connected to MEMC, which provides all signals and refresh operations for a wide variety of standard DRAMs. A Logical to Physical Address Translator maps the Physical memory into a 32MBylc Logical address space (with three levels of protection) allowing Virtual Memory and Multi-Tasking operations to be implemented. Fast "page mode" DRAM accesses are used to maximise memory bandwidth.

MEMC supports Direct Memory Access (DMA) read operations with a set of programmable DMA Address Generators, which provide a circular buffer for Video data, a linear buffer for Cursor data, and multiple buffers for Sound data.

Reference Number : 0460,019

Date Published : 30th September 1986

Manufacturer : Acorn

Platform : MEMC

Format : Spiral bound; 73 pages